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1 p/n:pm0342 rev. 1.4, nov. 07, 1998 MX98741 xrc 100 base-tx/fx repeater controller 1.0 features ? eight 100 base-tx/fx ports; each port individually configurable to tx or fx ? direct interface with analog clock generation/recov- ery chips ? three media independent interface (mii) ? expandable to increase number of repeater ports ? low latency design simplified high port number class ii repeater implementation ? management features accessible through mii or se- rial ports ? all ports can be separately isolated or partitioned in reponse to fault conditions ? conforms to ieee 802.3u repeater unit specifica- tion ? led display for tx/fx port activities and collisions ? 208-pin, cmos device in pqfp package 2.0 general description the MX98741 (100base-tx repeater controller, xrc) is a 208-pin pqfp device that interfaces directly with offshell clock generation/recovery chips. eight ports can be configured as 100 base-tx or fx ports individually. three additional ports have media independent inter- faces (mii) which allow easy connection of management and bridge devices. the expansion port allows multiple xrcs to be linked together to form a repeater of high port counts. leds are provided for visual monitoring of tx/fx port activities and collisions. the xrc's design inserts minimum delay between the tx/fx ports and the expansion port. a master-slave type arbitration is also implemented to shorten the communciation time among multiple xrcs. as a re- sult, design for class ii stackable hub is greatly simpli- fied. control functions and management status are imple- mented through internal registers. these registers are accessed via either standard mii management interface (mdc, mdio) or several serial ports. these serial ports are accessed easily by hardware for debugging and configuration purposes. a dedicated management chip can also utilize these serial ports to access the xrc.
2 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 3.0 pin configuration 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 vcc rsclk3 sigdet3 rdat30 rdat31 rdat32 rdat33 rdat34 gnd gnd tdat30 tdat31 tdat32 tdat33 tdat34 gnd gnd rsclk4 sigdet4 vcc rdat40 rdat41 rdat42 rdat43 rdat44 gnd tdat40 tdat41 tdat42 tdat43 tdat44 rsclk5 sigdet5 rdat50 rdat51 rdat52 rdat53 rdat54 vcc vcc tdat50 tdat51 tdat52 tdat53 tdat54 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 gnd sigdet2 rsclk2 gnd tdat14 tdat13 tdat12 tdat11 tdat10 vcc rdat14 rdat13 rdat12 rdat11 rdat10 vcc sigdet1 rsclk1 actp7 actp6 actp5 actp4/xrcadd4 vcc actp3/xrcadd3 actp2/xrcadd2 actp1/xrcadd1 actp0/xrcadd0 gnd anyact bdatenl extcrs jami jamo gnd efat4 edat3 edat2 edat1 edat0 vcc vcc tdat04 tdat03 tdat02 tdat01 tdat00 rdat04 rdat03 rdat02 rdat01 rdat00 gnd gnd rsclk6 sigdet6 rdat60 rdat61 rdat62 rdat63 rdat64 tdat60 tdat61 tdat62 tdat63 tdat64 gnd rsclk7 sigdet7 rdat70 rdat71 rdat72 rdat73 rdat74 gnd tdat70 tdat71 tdat72 tdat73 tdat74 vdd vcc xactled0 xactled1 xactled2 xactled3 xactled4 xactled5 xactled6 xactled7 gnd vcc regck regltch gnd rdxwr pidisi ptscen jbflo partnk isc gnd rsclko sigdeto gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 gnd gnd mdc mdio crsc rxdvc txerc txdc3 txdc2 txdc1 txdc0 txenc vcc rxclkj col rxer rxd3 rxd2 rxd1 rxd0 gnd txclk coclk vcc crse rxdvb txerb txdb3 txdb2 txdb1 txdb0 txenb gnd crsa rxdva txera txda3 txda2 txda1 txda0 txena tdat24 tdat23 tdat22 MX98741 gnd scrctrl resetl xcoled test tsel gnd tdat21 tdat20 rdat24 rdat23 rdat22 rdat21 rdat20 gnd
3 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 4.0 pin description table 4-1 pin description for MX98741 a. mx data transceiver (am78965/am78966 or mc68836), 98 pins pad # name i/o description 59-63 tdat[0:7][0:4] o, exp transmit data. these five outputs are 4b/5b encoded transmit 96-100 data symbols, driven at the rising edge of txclk. 111-115 tdat4 is the most significant bit. 167-171 183-187 197-201 9-13 23-27 135 txclk i, ttl transmit clock. this pin supplies the frequency reference to the transmit logic. it should be driven by an external 25 mhz crystal-controlled clock source. 54-58 rdat[0:7][0:4] i, ttl receive data. these 5-bit parallel data symbols from transceiver 90-94 are latched by the rising edge of rsclk. 106-110 rdat4 is the most significant bit. 160-164 177-181 190-194 4-8 17-21 50,87 rsclk[0:7] i, ttl recovered sumbol clock. this is a 25 mhz clock, which is derived 102,158 from the clock synchroniztion pll circuit. 174,188 2,15 51,88 sigdet[0:7] i, ttl signal detect. this signal indicates that the received signal is above 103,159 the detection threshold and will be used for the link test state 175,189 machine. 3,16 134 coclk i, ttl core clock. 50m clock input used by repeater core.
4 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 b. expansion port, 18 pins pad # name i/o description 72 jamo o, ttl forced jam out. active high. the ord f orced jam signals ex- clude jami input) controlled by carrier integrity monitor of each port. if collision occurs inside the xrc, this pin is also asserted. 73 jami i, schm forced jam input. active high. asserted by external arbiter, and xrc will generate jam patterns to all its ports. note : glitch on jami and edatenl may cause internal state machine malfunction. 75 edatenl i, schm enable expansion data. active low. asserted by an external arbitor. xrc will drive data into edat. 66-70 edat[0:4] i/o, exp expansion data. bidirectional 5-bit wide data. by default, edat is an input. when edatenl is low, edat changed from input mode to output mode. internally pull-up. 84-86 actp[5:8] o, ttl activity out. this is the activity of port 5..8 synchronous to coclk (50m clock used by core). it also serves as data framing signal for the packet on edat. actp leads edat's /j/k/ pattern by more than 80 ns and deasserted 40ns after the /t/r/ or the last byte of jam patterns. 78-81, 83 actp[0:4] i/o, ttl activity out/physical address. when resetl goes high, value /xrcadd[0:4] on actp[0;4] will be latched into internal buffer as physical address of xrc. after reset, these five pins have the same function as actp[5:8]. 76 anyact o, ttl any activity. active high. the ord a ctp[7:0] and txen a to c. this is used as an indication that an xrc is ready to drive data into edat. 74 extcrs i, schm e xternal carrier sense. active high. asserted by an external arbitor indicating activity from other xrc's at the expansion port. c. miscellaneous pins, 2 pins 204 resetl i, schm reset. active low. this signal is output by the system to reset all the logic on the chip. 203 scrctrl i, ttl scrambler control. if high, the scrambler/descrambler of each port is individually controlled by mii register 17. if low, the scrambler/ descrambler is bypassed in all the ports.
5 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 d. register access pins, 8 pins pad # name i/o description 47 partlnk o, ttl partition/link status. this pin shows the status of internal register #18 in round-robin fashion starting at port 0 partition status and ending at port7 link status after regltch is deasserted. 46 jbflo o, ttl jabber/buffer status. this pin shows the status of internal register #19 in round-robin fashion starting at port 0 jabber status and ending at port 7 elastic buffer over/underflow status after regltch is deasserted. 45 ptscen i/o, ttl port/scrambler enable. if rdxwr is high, each port's enable/dis- able status (register #17) will be displayed at the rising edge of regck in round-robin fashion starting at port 0 port 0 enable sta- tus and ending at port 7 scrambler enable status after regltch is deasserted. if rdxwr is low, 16-bit data can be written into the xrc at the rising edge of regck in round-robin fashion starting at port 0 port enable signal and ending at port 7 scrambler enable after regltch is asserted high. internally pull-up. 44 pidis i/o, ttl partition/isolation disable. if rdxwr is high, each port's partition/ isolation disable status will be displayed at the rising edge of regck in round-robin fashion starting at port 0 partition disable status and ending at port7 isolation disable status after regltch is deasserted. if rdxwr is low, 16-bit data can be written into the xrc at the rising edge of regck in round-robin fashion starting at port 0 partition disable status and ending at port 7 isolation dis- able status after regltch is asserted high. internally pull-down. 48 iso o, ttl isolation. active high. each port's isolation status will be displayed at the rising edge of regck in round-robin fashion starting at port0 after regltch is deasserted. 43 rdxwr i, ttl read/write. high indicates "read" mode; register is being read out. regltch is output. low indicates "write" mode; control reg- isters are being written and regltch is input. when rdxwr is programmed to "write" mode, internal "read" status machine will be reset immediately. 41 regltch i/o, ttl register latch. an output if rdxwr is high; an input if rdxwr is low. at the rising edge of regck, partlnk, jbflo, ptscen, pidis, iso display bit 0 status of corresponding registers, at the rising edge of next regck, bit 1 status is displayed, etc. after bit 15 is displayed, regltch is asserted at the rising edge of next regck. note : both data and regltch are driven at the falling edge of regck inside the xrc. to make sure the data setup time, it is strongly recommended that the frequency of regck is below 12.5 mhz. internally pull-down. 40 regck i, ttl register clock. a clock used as reference to display various sta- tus of each port or to latch control information inside xrc. the recommended clock's frequency is below 12.5mhz.
6 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 e. led pins, 9 pins pad # name i/o description 30-37 xactled[0:7] o, ttl activity led. active low. this pin provides a minimum 80ms on time (low) and 20ms off time (high) for activities on each port. external buffers are necessary to drive leds. 205 xcoled o, mii collision led. this pin is capable of driving led directly to display activity status. the on (active low) time and off (active high) time of led's is 80ms and 20ms respectively. f. media independent interface (mii), 33 pins 116 txena i, ttl transmit enable mii a. synchronous to the txclk's rising edge. it is asserted by the mac with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. 117-120 txda[0:3] i, ttl transmit data mii a. synchronous to the txclk's rising edge. for each txclk period in which txena is asserted, txda[3:0] are also driven by the mac. while txena is de-asserted, the value of txda[3:0] is ignored. txda3 is the most significant bit. 121 txera i, ttl transmit error mii a. synchronous to the txclk's rising edge. when txera is asserted for one or more txclk period while txena is also asserted, one or more "halt" symbols will present at tdat4_0. 122 rxdva o, ttl receive data valid mii a. synchronous to rxclk's rising edge. this signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame delim- iter. high impedance after reset. 123 crsa o, ttl carrier sense mii a. in tx mode, synchronous to rxclk. this pin is asserted when (1) the receiving medium is not idle, or (2) the transmitting medium is not idle in the half-duplex mode. high im- pedance after reset. 153 mdio i/o, ttl management data input/output. a bi-directional signal. after re- set, this pin is in high-impedance state. the selection of input/ output direction is based on ieee 802.3u management functions (section 22.2.4). low after reset due to internally pull-down. when rdxwr is low (i.e. write operation, mdio will be forced to low to disable the function of mdc and mdio. i.e. programming internal registers through register access pins owns higher priority.
7 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 f. media independent interface (mii, continued) pad # name i/o description 125 txenb i, ttl transmit enable mii b. synchronous to the txclk's rising edge. it is asserted by the mac with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. 126-129 txdb[0:3] i, ttl transmit data mii b. synchronous to the txclk's rising edge. for each txclk period in which txenb is asserted, txdb[3:0] are also driven by the mac. while txenb is de-asserted, the value of txdb[3:0] is ignored. txdb3 is the most significant bit. 130 txerb i, ttl transmit error mii b. synchronousto the txclk's rising edge. when txerb is asserted for one or more txclk period while txenb is also asserted, one or more "halt" symbols will present at tdat4_0. 131 rxdvb o, ttl receive data valid mii b. synchronous to rxclk's rising edge. this signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame deliminter. high impedance after reset. 132 crsb o, ttl carrier sense mii b. in tx mode, synchronous to rxclk. this pin is asserted when (1) the receiving medium is not idle, or (2) the transmitting medium is not idle in the half-duplex mode. high im- pedance after reset. 145 txenc i, ttl transmit enable mii c. synchronous to the txclk's rising edge. it is asserted by the mac with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented. 146-149 txdc[0:3] i, ttl transmit data mii c. synchronous to the txclk's rising edge. for each txclk period in which txenc is asserted, txdc[3:0] are also driven by the mac. while txenc is de-asserted, the value of txdc[3:0] is ignored. txdc3 is the most significant bit. 150 txerc i, ttl transmit error mii c. synchronousto the txclk's rising edge. when txerc is asserted for one or more txclk period while txenc is also asserted, one or more "halt" symbols will present at tdat4_0 151 rxdvc o, ttl receive data valid mii c. synchronous to rxclk's rising edge. this signal remains asserted through the whole frame, starting with the start-of-frame delimiter and excluding any end-of-frame deliminter. high impedance after reset. 152 edatact o, ttl expansion data activity. when xrc is outputing data onto expan- sion edat, this pin will be asserted high. user can use this pin to control external edat bus switch in case multiple hubs applica- tion is necessary.
8 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 pad # name i/o description 141 rxer o, exp receive error. synchronous to rxclk's rising edge. while rxdv is asserted, i.e. a frame is being received, this signal is asserted if any coding error is detected. high-impedence after reset. 143 rxclk o, mii receive clock mii. 25 mhz continuous clock that provides the timing reference for the transfer of the rxdv, rxd and rxer sig- nals. high-impedance after reset. 137-140 rxd[0:3] o, mii receive data mii. synchronous to rxclk's rising edge. for each rxclk period in which rxdv is asserted, rxd[3:0] should be latched by the mac. while rxdv is deasserted, rxd[3:0] are the nibbles 5b/4b decoded from rdat[4:0]. rxd3 is the most signifi- cant bit. high-impedance after reset. 142 col o, exp collision mii. this signal is asserted if both the receiving media and txen are active. high-impedance after reset. 154 mdc i, ttl management data clock. the timing reference for mdio. the minumum high and low times are 200 ns each. no limitation on the maximum high and low time. g. power/ground/test/loopback, 39 pins 206 test i, ttl test. industrial test pin. set to 0 or left unconnected for normal operation. when programmed to logic 1, xrc is in test mode. internal pulldown. 207 tsel i, ttl test mode select. when test is high and tsel is low, xrc is in "real time counter" mode; when test is high and tsel is high, xrc is in "test mode counter" mode. internally pull down. 1,14,22, 38,42,49 52,53,71, 77,101 104,105, 124,136, gnd ground. 155,156, 165,166, 173,182, 202,208 28,29, 39,64, 65,82, 89,95, vcc 5v power supply. 133,144, 157,176, 195,196
9 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 5.0 functional & operation description 5.1 minimum and maximum mode application xrc arb dt& pmd port 0 figure 5-1 minimum mode operation for xrc xrc dt& pmd port 7 dt& pmd port 8 dt& pmd port 15 bridge mgmnt bridge t4 pmd tx pmd xrc mii_a mii_c mii_b arbitor dt& pmd port 0 figure 5-2 maximum mode operation for xrc xrc dt& pmd port 7 dt& pmd port 8 dt& pmd port 15
10 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 5.2 internal registers there are two ways to access the xrc internal regis- ters. all the registers can be accessed through mii's mdc and mdio. although xrc connects to multiple 100-tx phy's, they are all identical. each xrc has only one phy address as defined by actp[4:0] pins. if multiple xrc's are on the same mdio bus, each of them should have different phy address. other non-xrc phy de- vices (e.g. t4) are also allowed to be managed with the same management interface as long as phy address of each device is distinct. another way to access registers is through register ac- cess pins. register 17 (scrambler enable and port enable), register 18 (link status, partition status), register 19 (elastic buffer status and jabber status), register 20 (isolation status), register 21 (isolation disable and partition disable) can also be read through ptscen, partlnk, jbflo, iso and pidis, respec- tively. the exception are register 0 (command regis- ter), register 1 (status register), and register 16 (port reset register) which can only be accessed through mdc and mdio. the register access pins facilitate a simple read/write protocol suitable for hardware-only configuration and status display design.
11 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 a. command register (register #0) (r/w) table 5-1 control register bit definition bit(s) name description r/w 0.15 reset 1 : phy reset. a 240ns reset pulse will be generated to reset xrc internal logic. r/w 0 : normal operation sc 0.14 loop back 1 : enable loopback mode. 0 : disable loopback mode. the default setting is 0. r/w 0.13 speed selection forced to 1 and indicate 100 mb/s. write 0 to this bit has no effect. r 0.12 auto-negotiation enable forced to 0 and indicate that auto-negotiation process is disabled. write 1 to this bit has no effect. r 0.11 power-down 1 : pow er-down. coclk and txclk for each port will be disabled. clock for management block will keep running. during power-down, all state machines will be reset to its default state. 0 : normal operation. r/w 0.10 isolate 1 : electrically isolate phy from mii 0 : normal operation r/w 0.9 restart forced to 0 and indicate that auto-negotiation process auto-negotiation is disable. write 1 to this bit has no effect. r 0.8 duplex mode forced to 0 and indicate that only half duplex is available. write 1 to this bit has no effect. r 0.7 collision test 1 : enable col signal test. the phy will assert the col signal within 5120 ns in response to the assertion of txen. while this bit is set to one, the phy will deassert the col signal within 40 ns in response to the deassertion of txen. 0 : normal operation. set to 0 after power on reset. r/w 0.6:0 reserved value 0 will be read when one tries to read these bits. r
12 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 b. status register (register #1) (r) table 5-2 status register bit definition bit(s) name description r/w 1.15 100base-t4 forced to 0 and indicates that xrc is not able to perform 100base-t4. r 1.14 100base-x forced to 0 and indicates that xrc is not able to perform full duplex 100base-x full duplex. r 1.13 100base-x forced to 1 and indicates that xrc is able to perform half duplex 100base-x half duplex. r 1.12 10 mb/s full duplex forced to 0 and indicates that xrc is not able to perform 10 mb/s full duplex. r 1.11 10 mb/s half duplex forced to 0 and indicates that xrc is not able to perform 10 mb/s half duplex. r 1.10:6 reserved value 0 will be released by xrc when read. r 1.5 auto-negotiation complete forced to 0. r 1.4 remote fault forced to 0. r 1.3 auto-negotiation ability forced to 0. r 1.2 link status 1 : all ports are link up. 0 : any port is link fail. will be set to 1 after this port is read. r 1.1 jabber detect 1 : jabber condition in any port is detected. 0 : no jabber condition detected for all ports r 1.0 extended capability forced to 1. r
13 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 c. port reset register (register #16) (r/w) table 5-3 port reset register bit definition bit(s) name description r/w 16.15:8 reserved ignored when read. r 16.7 resetp7 1 : reset port 7's logic. 0 : not reset port 7's logic. power on low. r/w 16.6 resetp6 1 : reset port 6's logic. 0 : not reset port 6's logic. power on low. r/w 16.5 resetp5 1 : reset port 5's logic. 0 : not reset port 5's logic. power on low. r/w 16.4 resetp4 1 : reset port 4's logic. 0 : not reset port 4's logic. power on low. r/w 16.3 resetp3 1 : reset port 3's logic. 0 : not reset port 3's logic. power on low. r/w 16.2 resetp2 1 : reset port 2's logic. 0 : not reset port 2's logic. power on low. r/w 16.1 resetp1 1 : reset port 1's logic. 0 : not reset port 1's logic. power on low. r/w 16.0 resetp0 1 : reset port 0s logic. 0 : not reset port 0s logic. power on low. r/w
14 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 d. port control register (register #17) (r/w) table 5-4 port control register bit definition bit(s) name description r/w 17.15 screnp7 1 : enable scrambler/descrambler at port 7 0 : disable scrambler/descrambler at port 7 the default value after power on is 1. r/w 17.14 screnp6 1 : enable scrambler/descrambler at port 6 0 : disable scrambler/descrambler at port 6 the default value after power on is 1. r/w 17.13 screnp5 1 : enable scrambler/descrambler at port 5 0 : disable scrambler/descrambler at port 5 the default value after power on is 1. r/w 17.12 screnp4 1 : enable scrambler/descrambler at port 4 0 : disable scrambler/descrambler at port 4 the default value after power on is 1. r/w 17.11 screnp3 1 : enable scrambler/descrambler at port 3 0 : disable scrambler/descrambler at port 3 the default value after power on is 1. r/w 17.10 screnp2 1 : enable scrambler/descrambler at port 2 0 : disable scrambler/descrambler at port 2 the default value after power on is 1. r/w 17.9 screnp1 1 : enable scrambler/descrambler at port 1 0 : disable scrambler/descrambler at port 1 the default value after power on is 1. r/w 17.8 screnp0 1 : enable scrambler/descrambler at port 0 0 : disable scrambler/descrambler at port 0 the default value after power on is 1. r/w 17.7 enp7 1 : enable rx/tx functions at port 7. 0 : disable rx/tx functions at port 7. the default value after power on is 1. r/w 17.6 enp6 1 : enable rx/tx functions at port 6. 0 : disable rx/tx functions at port 6. the default value after power on is 1. r/w 17.5 enp5 1 : enable rx/tx functions at port 5. 0 : disable rx/tx functions at port 5. the default value after power on is 1. r/w
15 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 table 5-4 port control register bit definition (continued) bit(s) name description r/w 17.4 enp4 1 : enable rx/tx functions at port 4. 0 : disable rx/tx functions at port 4. the default value after power on is 1. r/w 17.3 enp3 1 : enable rx/tx functions at port 3. 0 : disable rx/tx functions at port 3. the default value after power on is 1. r/w 17.2 enp2 1 : enable rx/tx functions at port 2. 0 : disable rx/tx functions at port 2. the default value after power on is 1. r/w 17.1 enp1 1 : enable rx/tx functions at port 1. 0 : disable rx/tx functions at port 1. the default value after power on is 1. r/w 17.0 enp0 1 : enable rx/tx functions at port 0. 0 : disable rx/tx functions at port 0. the default value after power on is 1. r/w
16 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 e. link and partition status register (register #18) (r) table 5-5 link and partition status register bit definition bit(s) name description r/w 18.15 linkp7 1 : link status is ok at port 7 0 : link status is fail at port 7 status is updated at every txclk clock. r 18.14 linkp6 1 : link status is ok at port 6 0 : link status is fail at port 6 status is updated at every txclk clock. r 18.13 linkp5 1 : link status is ok at port 5 0 : link status is fail at port 5 status is updated at every txclk clock. r 18.12 linkp4 1 : link status is ok at port 4 0 : link status is fail at port 4 status is updated at every txclk clock. r 18.11 linkp3 1 : link status is ok at port 3 0 : link status is fail at port 3 status is updated at every txclk clock. r 18.10 linkp2 1 : link status is ok at port 2 0 : link status is fail at port 2 status is updated at every txclk clock. r 18.9 linkp1 1 : link status is ok at port 1 0 : link status is fail at port 1 status is updated at every txclk clock. r 18.8 linkp0 1 : link status is ok at port 0 0 : link status is fail at port 0 status is updated at every txclk clock. r 18.7 partp7 1 : port 7 has been partitioned 0 : port 7 has not been partitioned status is updated every 40 ns. r 18.6 partp6 1 : port 6 has been partitioned 0 : port 6 has not been partitioned status is updated every 40 ns. r 18.5 partp5 1 : port 5 has been partitioned 0 : port 5 has not been partitioned status is updated every 40 ns. r
17 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 table 5-5 link and partition status register bit definition (continued) bit(s) name description r/w 18.4 partp4 1 : port 4 has been partitioned 0 : port 4 has not been partitioned status is updated every 40 ns. r 18.3 partp3 1 : port 3 has been partitioned 0 : port 3 has not been partitioned status is updated every 40 ns. r 18.2 partp2 1 : port 2 has been partitioned 0 : port 2 has not been partitioned status is updated every 40 ns. r 18.1 partp1 1 : port 1 has been partitioned 0 : port 1 has not been partitioned status is updated every 40 ns. r 18.0 partp0 1 : port 0 has been partitioned 0 : port 0 has not been partitioned status is updated every 40 ns. r
18 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 f. elastic buffer over/underflow and jabber status register (register #19) (r) table 5-6 elastic buffer over/underflow and jabber register bit definition bit(s) name description r/w 19.15 ebouf7 1 : elastic buffer over/underflow at port 7 0 : normal condition. clear to 0 by resetl (or resetp7). r 19.14 ebouf6 1 : elastic buffer over/underflow at port 6 0 : normal condition. clear to 0 by reset (or resetp6). r 19.13 ebouf5 1 : elastic buffer over/underflow at port 5 0 : normal condition. clear to 0 by reset (or resetp5). r 19.12 ebouf4 1 : elastic buffer over/underflow at port 4 0 : normal condition. clear to 0 by reset (or resetp4). r 19.11 ebouf3 1 : elastic buffer over/underflow at port 3 0 : normal condition. clear to 0 by reset (or resetp3). r 19.10 ebouf2 1 : elastic buffer over/underflow at port 2 0 : normal condition. clear to 0 by reset (or resetp2). r 19.9 ebouf1 1 : elastic buffer over/underflow at port 1 0 : normal condition. clear to 0 by reset (or resetp1). r 19.8 ebouf0 1 : elastic buffer over/underflow at port 0 0 : normal condition. clear to 0 by reset (or resetp0). r 19.7 jabp7 1 : receive jabber active at port 7 0 : no jabber condition at port 7 r 19.6 jabp6 1 : receive jabber active at port 6 0 : no jabber condition at port 6 r 19.5 jabp5 1 : receive jabber active at port 5 0 : no jabber condition at port 5 r 19.4 jabp4 1 : receive jabber active at port 4 0 : no jabber condition at port 4 r 19.3 jabp3 1 : receive jabber active at port 3 0 : no jabber condition at port 3 r
19 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 table 5-6 elastic buffer over/underflow and jabber register bit definition (continued) bit(s) name description r/w 19.2 jabp2 1 : receive jabber active at port 2 0 : no jabber condition at port 2 r 19.1 jabp1 1 : receive jabber active at port 1 0 : no jabber condition at port 1 r 19.0 jabp0 1 : receive jabber active at port 0 0 : no jabber condition at port 0 r g. isolation status register (register #20) (r) table 5-7 isolation status register bit definition bit(s) name description r/w 20.15 iso7 1 : port isolation is occuring at port 7, 0 : port isolation is not occuring at port 7. set to 1 by cim state machine, cleared to 0 by asserting resetl pin or writing to port reset register or by cim state machine. r 20.14 iso6 1 : port isolation is occuring at port 6, 0 : port isolation is not occuring at port 6. r 20.13 iso5 1 : port isolation is occuring at port 5, 0 : port isolation is not occuring at port 5. r 20.12 iso4 1 : port isolation is occuring at port 4, 0 : port isolation is not occuring at port 4. r 20.11 iso3 1 : port isolation is occuring at port 3, 0 : port isolation is not occuring at port 3. r 20.10 iso2 1 : port isolation is occuring at port 2, 0 : port isolation is not occuring at port 2. r 20.9 iso1 1 : port isolation is occuring at port 1, 0 : port isolation is not occuring at port 1. r 20.8 iso0 1 : port isolation is occuring at port 0, 0 : port isolation is not occuring at port 0. r 20.7:0 reserved ignored while read. r
20 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 h. isolation/partition disable register (register #21) (r/w) table 5-8 isolation/partition disable register bit definition bit(s) name description r/w 21.15 isodis7 1 : port 7 isolation function is disabled 0 : port 7 isolation function is not disabled. the default value is 0 after reset. r/w 21.14 isodis6 1 : port 6 isolation function is disabled 0 : port 6 isolation function is not disabled. the default value is 0 after reset. r/w 21.13 isodis5 1 : port 5 isolation function is disabled 0 : port 5 isolation function is not disabled. the default value is 0 after reset. r/w 21.12 isodis4 1 : port 4 isolation function is disabled 0 : port 4 isolation function is not disabled. the default value is 0 after reset. r/w 21.11 isodis3 1 : port 3 isolation function is disabled 0 : port 3 isolation function is not disabled. the default value is 0 after reset. r/w 21.10 isodis2 1 : port 2 isolation function is disabled 0 : port 2 isolation function is not disabled. the default value is 0 after reset. r/w 21.9 isodis1 1 : port 1 isolation function is disabled 0 : port 1 isolation function is not disabled. the default value is 0 after reset. r/w 21.8 isodis0 1 : port 0 isolation function is disabled 0 : port 0 isolation function is not disabled. the default value is 0 after reset. r/w 21.7 pardis7 1 : port 7 parition function is disbled. 0 : port 7 partition function is not disabled. the default value is 0 after reset. r/w 21.6 pardis6 1 : port 6 parition function is disbled. 0 : port 6 partition function is not disabled. the default value is 0 after reset. r/w 21.5 pardis5 1 : port 5 parition function is disbled. 0 : port 5 partition function is not disabled. the default value is 0 after reset. r/w 21.4 pardis4 1 : port 4 parition function is disbled. 0 : port 4 partition function is not disabled. the default value is 0 after reset. r/w
21 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 table 5-8 isolation/partition disable register bit definition (continued) bit(s) name description r/w 21.3 pardis3 1 : port 3 parition function is disbled. 0 : port 3 partition function is not disabled. the default value is 0 after reset. r/w 21.2 pardis2 1 : port 2 parition function is disbled. 0 : port 2 partition function is not disabled. the default value is 0 after reset. r/w 21.1 pardis1 1 : port 1 parition function is disbled. 0 : port 1 partition function is not disabled. the default value is 0 after reset. r/w 21.0 pardis0 1 : port 0 parition function is disbled. 0 : port 0 partition function is not disabled. the default value is 0 after reset. r/w note : physical address input from actp[4:0] during resetl is asserted will be stored at bit 4:0 of register #31. 6.0 absolute maximum ratings table 6-1 absolute maximum rating for MX98741 rating value supply voltage (vcc) 4.75v to 5.25v dc input voltage (vin) -0.5v to vcc+0.5v dc output voltage (vout) -0.5v to vcc+0.5v storage temperature range (tstg) -55 c to 150 c power dissipation (pd) 750 mw esd rating (rzap = 1.5k, czap = 100pf) 2000v notice : 1. stresses greater than those listed under absolute maximum ratings may cauase permanent dam- age to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximum rating conditions for ex- tended period may affect reliability. 2. preliminary, subject to change.
22 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 7.0 dc characteristics table 7-1 dc characteristics for MX98741 symbol parameter conditions min. max. unit a. supply current icc average active (txing coclk = 50mhz /rxing) supply current vin = switching - 50 ma iccidle average idle supply current coclk = 50mhz vin=vcc/gnd - tbd (note) ma idd static idd current coclk=undriven - tbd (note) ua note : these two parameters will be measured while dc/ac characterization is proceeding. symbol parameter conditions min. max. unit b. ttl inputs, outputs, tri-states vil maximum low level input voltage gnd = 0v - 0.8 v vih minimum high level input voltage 2.0 vcc+0.5 v iin input current vi=vcc/gnd -1.0 1.0 ua voh minimum high level output voltage ioh = -2ma 2.4 - v vol maximum low level output voltage iol = 2ma - 0.4 v ioz maximum tri-state output leakage current vout=vcc/gnd -10.0 10.0 ua c. exp outputs, tri-states voh minimum high level output voltage ioh = -4ma 2.4 - v vol maximum low level output voltage iol = 4ma - 0.4 v vil maximum low level input voltage - 0.8 v vih minimum high level input voltage 2.0 - v ioz maximum tri-state output leakage current vout=vcc/gnd -10.0 10.0 ua d. mii inputs, outputs, tri-states voh minimum high level output voltage ioh = -8ma 2.4 - v vol maximum low level output voltage iol = 8ma - 0.4 v vil maximum low level input voltage - 0.8 v vih minimum high level input voltage 2.0 - v ioz maximum tri-state output leakage current vout=vcc/gnd -10.0 10.0 ua
23 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 table 7-1 dc characteristics for MX98741 (continued) symbol parameter conditions min. max. unit e. ttl input with schmitt trigger vil maximum low level input voltage - 0.6 v vih minimum high level input voltage 2.7 - v note : 1.all parameters listed in category a/b/c/d are prelimi- nary, subject to change. after wafer is out, the value measured on tester will be the finalized voltage char- acteristics. 2.for mii port, see item f in next page for one's refer- ence. symbol parameter conditions min. max. unit f. input current limits for mii iih input high current with vi = 5.25 volt all except col, mdc, mdio(note 1) - 200 ua col (note 2) - 20 ua mdc (note 3) - 20 ua mdio (note 4) - 3000 ua mdio (note 5) - 20 ua iil input low current with vi = 0.00 volt all except col, mdc, mdio(note 1) -20 - ua col (note 2) -200 - ua mdc (note 3) -20 - ua mdio (note 4) -180 - ua mdio (note 5) -3800 - ua iiq input quiescent current with vi = 2.4 volt mdio (note 4) - 1450 ua mdio (note 5) -1450 - ua note1 : measured at input of reconcilation sublayer for crss, rxd[3:0], rxclk, rxdvs, rxer, and txclk. measured at inputs of xrc for txd[3:0], txen, and txer. note 2 : measured at input of reconciliation sublayer. note 3 : measured at input of xrc. note 4 : measured at input of sta. note 5 : measured at input of xrc which cn be attached via the mechanical interface specified in sec tion 22.6 in [1]. caution : input current limit is only for board designers reference. in MX98741, we will not use this specification to verify the input signals provided by stimulus patterns.
24 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 symbol description min. max. unit t01 period for mdc 400 - ns t02 high time for mdc 160 - ns t03 low time for mdc 160 - ns t04 mdio setup to mdc rising edge (write command) 10 - ns t05a mdio hold to mdc rising edge (write command) 10 - ns t05b mdio hold to mdc rising edge (read command) 5 10 ns 8.0 ac characteristics and waveforms a. media independent interface t05 mdc t02 mdio t04 figure 8-1 mdio timing relationship to mdc t01 t03
25 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 symbol description min. max. unit t11 rxclk period (note 1) 40 40 ns t12 rxclk high time 19 - ns t13 rxclk low time 17 - ns t14 rxd[3:0]/rxdvs/rxer setup time to rxclk rising edge (note 2) 10 - ns t15 rxd[3:0]/rxdvs/rxer hold time to rxclk rising edge (note 2) 15 - ns note 1 : the accurate rxclk frequency shall be 25mhz +/- 100 ppm. note 2 : the setup time of an mii signal relative to an mii clock edge is defined as the length of time between when the signal exits and remains out of the switching region and when the clock en- ters the switching region. the hold time of an mii signal relative to an mii clock edge is de- fined as the length of time between when the clock exits the switching region and when the signal enters the switching region. t15 rsclk t12 rxd[3:0] rxdv rxer t14 figure 8-2 receive signal timing relationships at the mii t11 t13
26 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 symbol description min. max. unit t21 txclk period (note 1) 40 40 ns t22 txclk high time 0.35*t21 0.65*t21 ns t23 txclk low time 0.35*t21 0.65*t21 ns t24 txd[3:0]/txens/txers setup time to txclk rising edge (note 2) 10 - ns t25 txd[3:0]/txens/txers hold time to txclk rising edge (note 2) 10 - ns note 1 : the accurate txclk frequency shall be 25 mhz +/- 100 ppm. note 2 : the setup time of an mii signal relative to an mii clock edge is defined as the length of time between when the signal exits and remains out of the switching region and when the clock en- ters the switching region. the hold time of an mii signal relative to an mii clock edge is de- fined as the length of time between when the clock exits the switching region and when the signal enters the switching region. t25 txclk t22 txd[3:0] txen txer t24 figure 8-3 trannsmit signal timing relationships at the mii t21 t23
27 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 b. data transceiver interface symbol description min. max. unit t31 tdat[4:0] to txclk rise delay time 5 15 ns note : tested under 30pf loading. symbol description min. max. unit t41 rsclk period (note 1) 40 40 ns t42 rsclk pulse width high 10 - ns t43 rsclk pulse width time 20 - ns t44 rdat[4:0] valid to rsclk rise 2 - ns t45 rsclk rise to rdat[4:0] invalid 4 - ns note 1 : the accurate rxclk frequency shall be 25 mhz +/- 100 ppm. t31 txclk tdat[4:0] figure 8-4 trannsmit signal timing relationships at the dt rsclk t42 rdat[4:0] figure 8-5 receive signal timing relationships at the dt t41 t43 t45 t44
28 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 symbol description min. max. unit t51 pulse width for resetl 2400 - ns t52 coclk period (note 1) 20 20 ns t53 coclk pulse width high 8 - ns t54 coclk pulse width low 8 - ns note 1 : the maximum frequency variation for coclk shold be less than 100ppm. coclk txclk resetl t53 t51 figure 8-6 timing relationship for coclk, txclk, and resetl t52 t54
29 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 d. status pins symbol description min. max. unit t61 regck period 50 - ns t62 regck pulse width high 12 - ns t63 regck pulse width low 12 - ns t64 regck falling to status valid - 10 ns t65 regck falling to status invalid - 12 ns t66 regck falls to regltch asserted (note 1) 5 10 ns note 1 : one can use regck rising edge to latch data in system application. note 2 : test under 30pf loading. t65 t66 regck regltch t62 partlnk jbflo ptscen pidis iso t64 figure 8-7 timing relationship for regck, regltch and round-robin status pins t61 t63
30 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 e. network interface pins symbol description min. max. unit t71 receiving port goes to idle to activate again (note) 100 - ns t72 listening port activate after other port idle (note) 100 - ns note : the restriction in ieee 802.3u specifiction is 96bt. i.e 960 ns. interframe gap time less than the value shown above may cause packet loss and internal state machine malfunction. listening port figure 8-8 receive signal timing relationships at the dt t72 receiving port t71
31 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 f. expansion port interface symbol description min. max. unit t81 txclk rising to anyact assert/deassert - 18 ns t82 txclk rising to jamo assert /deassert - 13 ns t83 anyact assert to edatenl assert (note) - 17 ns t84 txclk rising to edatoe assert - 25 ns t85a edat to txclk delay time (output by MX98741) 12 26 ns t85b edat to txclk hold time (input by MX98741) 4 - ns t86 edat to txclk setup time (input by MX98741) 2 - ns t87 edatenl asserted to txclk rising setup time 5 - ns note : if the external arbitor cannot generate edatenl signals within 35 ns form txclk rising edge (or 17 ns after anyact is asserted in figure 9-9) for some reason, edat has to be delayed by one txclk cycle. consequently, the longer the delay time changes the repeater from class ii to class i. a 7ns pal is suggested to be used for external arbitor to minimize the delay. anyact edatenl jami extcrs txclk figure 8-9 expansion port timing relationship jamo edatoe edat t82 t81 t83 t87 t82 t83 t81 t84 t86 /i/ /k/ t85 /j/ /d1/ /t/ /r/
32 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 revision history revision description page date 1.4 (1) 5.2 internal registers, register 0, 1, and 16 can only be accessed nov/07/1998 through mdc and md10. p.13 (2) delete the redundant page. p.21 (3) figure 8-6, delete t55. p.35 (4) figure 9-9, edat to txclk setup/hold time and edatenl to txclk rising edge setup time are added. p.38
33 p/n:pm0342 rev. 1.4, nov. 07, 1996 MX98741 10.0 package information 208-pin plastic quad flat pack item millimeters inches a 31.20 . 30 1.228 . 12 b 28.00 . 10 1.102 .004 c 28.00 . 10 1.102 . 004 d 31.20 . 30 1.228 . 012 e 25.35 .999 f 1.33 [ref.] .052 [ref.] g 1.33 [ref.] .052 [ref.] h .30 [typ.] .012 [typ.] i .65 [typ.] .026 [typ.] j 1.60 [ref.] .063 [ref.] k .80 . 20 .031 . 008 l .15 [typ.] .006 [typ.] m .10 max. .004 max. n 3.35 max. .132 max. o .10 min. .004 min. p 3.68 max. .145 max. note: each lead centerline is located within .25 mm[.01 inch] of its true position [tp] at maximum material condition. f n m k l j p o ecd 40 1 80 81 120 121 160 41 i h g b a
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